The present invention relates to an equalizer circuit and equalizing method and, more particularly, to an equalizer circuit and equalizing method for preventing waveform distortion and interference waves (noise) in multipath fading.
In data transmission of a high-speed radio ATM (Asynchronous Transfer Mode) system for multimedia mobile communication of 20 to 30 Mbps using a 5.2-GHz band, an equalizing function is used to prevent data quality degradation in multipath fading.
A technique using this equalizing function has been proposed by the present applicant/assignee. This technique proposes a radio data communication terminal for narrowband modulation system, in which a tap coefficient for an equalizer is set after a frequency offset value for operating a phase rotation means is obtained using, e.g., a shortest preamble.
As shown in FIG. 3, the equalizer circuit for performing the above equalizing function comprises a carrier sensor 6 for sensing the presence/absence of an input carrier and an equalizer unit 7 for receiving an output from the carrier sensor 6. The equalizer unit 7 is comprised of a memory unit 8, phase rotation unit 9, phase difference detector 10, average value detector 11, integrator 12, vector converter 13, transmission line characteristic estimating unit 14, a tap coefficient setting unit 15, and equalizer 16.
The carrier sensor 6 senses the presence/absence of a carrier in accordance with an RSSI (Received Signal Strength Indicator) signal Q representing the reception level from an RF (Radio Frequency) converter (not shown). The carrier sensor 6 then detects the start of a reception signal and outputs a carrier sense signal R to the equalizer unit 7 for a time interval from a time when detecting the start of reception data to a time when receiving a demodulation data end signal S of a one-pulse signal for stopping the equalizer unit 7.
The memory unit 8 receives a reception data signal P for an arbitrary period to control the output. The phase rotation unit 9 rotates the phase of the output signal from the memory unit 8 through a necessary angle. The phase difference detector 10 obtains the current angle and the angle of a PN (Pseudo Noise) code sequence obtained upon the lapse of one period. The phase difference detector 10 then obtains the difference between these two angles.
The average value detector 11 integrates the phase difference from the phase difference detector 10 a predetermined number of times. The average value detector 11 then divides the integrated value by the predetermined number of times to obtain the average value of the average phase difference per symbol. The integrator 12 integrates the average value from the average value detector 11 in units of symbols. The vector converter 13 converts the output from the integrator 12 into a real part amplitude value and an imaginary part amplitude value. The vector converter 13 outputs these amplitude values to the phase rotation unit 9.
The transmission line characteristic estimating unit 14 obtains the transmission line characteristics of the one-period PN code sequence for a preamble period using the signal obtained upon phase rotation in the phase rotation unit 9. The tap coefficient setting unit 15 obtains a tap coefficient necessary for the equalizer 16 in accordance with the transmission line characteristics obtained by the transmission line characteristic estimating unit 14. The tap coefficient setting unit 15 then sets the tap coefficient in the equalizer 16. The equalizer 16 equalizes the output from the phase rotation unit 9 using a filter having the tap coefficient set by the tap coefficient setting unit 15. The equalizer 16 outputs a demodulation data signal U. Reception processing is performed using this demodulation data signal U.
FIGS. 4A to 4F show the reception timings of a conventional phase shifter circuit shown in FIG. 3. In this case, the inactive interval of the reception data signal P is long.
The carrier sensor 6 determines the presence/absence of a carrier in accordance with the RSSI signal Q from the RF converter (FIG. 4B). The carrier sensor 6 then outputs the carrier sense signal R representing the start of the reception data signal P to the equalizer unit 7 (FIGS. 4A and 4C). Upon detecting the start of the reception data signal P, the equalizer unit 7 detects the frequency offset, estimates the transmission line characteristics, and sets the tap coefficient.
The equalizer 16 stores the preamble signal having the repeated PN code in the memory unit 8 and performs processing for a period of various initial settings (FIG. 4E) and has a delay accordingly. Upon completion of various initial settings in the equalizer 16, the demodulation data signal U is output (FIG. 4G). Upon completion of demodulation, the demodulation data end signal S is output to the carrier sensor 6 (FIG. 4F). At this time, the equalizer unit 7 is always operating in response to a system clock signal T (FIG. 4D) and therefore consumes power. In addition, a long inactive interval decreases the information bit rate.
FIGS. 5A to 5G show the reception timings of the conventional phase shifter circuit shown in FIG. 3. This exemplifies a short inactive interval of the reception data signal P.
The carrier sensor 6 determines the presence/absence of a carrier in accordance with the RSSI signal Q from the RF converter (FIG. 5B) and outputs the carrier sense signal R representing the start of the reception data signal P to the equalizer unit 7 (FIGS. 5A and 5C). The equalizer unit 7 detects a frequency offset, estimates the transmission line characteristics, and sets the tap coefficient upon detecting the start of the reception data signal P.
The equalizer 16 stores the preamble signal having the repeated PN code in the memory unit 8 and performs processing for a period of various initial settings (FIG. 5E) and has a delay accordingly. Upon completion of various initial settings in the equalizer 16, the demodulation data signal U is output (FIG. 5G). Upon completion of demodulation, the demodulation data end signal S is output to the carrier sensor 6 (FIG. 5F). At this time, the equalizer unit 7 is always operating in response to a system clock signal T (FIG. 5D) and therefore consumes power.
Since the inactive interval of the reception data signal P is short, a carrier detection signal β representing the leading edge of the carrier sense signal R cannot be detected upon receiving the next frame during a carrier sense period α. Therefore, the reception operation is performed every other frame, and the demodulation data signal U cannot normally be output.
In the above conventional equalizer circuit, a long inactive interval undesirably decreases the information bit rate. When the next frame is received during the processing period of the demodulation data with a short inactive interval, the carrier sense signal cannot be detected. Data is received every other frame, resulting in a reception error. Since the equalizer unit is always operating in response to the system clock signal, wasteful power is undesirably consumed.